By stacking transistors on top of one another, rather than laying them side by side on a flat chip, many electronic engineers are hopeful that vast amounts of computing power could be packed into tiny spaces, all while cutting energy use. So far, however, the ability to build these monolithic 3D integrated circuits has proven stubbornly difficult, largely because the fabrication processes required can damage the layers already in place.
Through new research published in Nature, Qing Cao and colleagues at the University of Illinois Urbana-Champaign have developed a new approach that sidesteps these problems, bringing high-performance 3D chips a step closer to reality.
Overheated stacks of transistors
Modern computer chips are built on thin wafers of silicon, with transistors (the ...
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