CMOS tagged posts

World-first spintronic p-bit on silicon chip points toward larger AI-ready p-computers

Spintronics P-computer ready for scale-up
Photograph of test chips fabricated on a silicon substrate using semiconductor integrated circuit manufacturing processes. Credit: Shunsuke Fukami, William A. Borders et al

A Japan–U.S. collaborative research team has demonstrated the world’s first integrated spintronic probabilistic bit, or p-bit, fabricated on a silicon chip using semiconductor manufacturing processes. The team, consisting of researchers from Tohoku University and the National Institute of Standards and Technology, experimentally verified the operation of the p-bit, a key building block for probabilistic, or p-, computers. The achievement provides a pathway toward large-scale spintronic p-computers for applications such as AI and machine learning.

Many emerging computational problems require efficient exploratio...

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Scientists smash record in stacking semiconductor transistors for large-area electronics

transistor
Credit: CC0 Public Domain

King Abdullah University of Science and Technology (KAUST; Saudi Arabia) researchers have set a record in microchip design, achieving the first six-stack hybrid CMOS (complementary metal-oxide semiconductor) for large-area electronics. With no other reported hybrid CMOS exceeding two stacks, the feat marks a new benchmark in integration density and efficiency, opening possibilities in electronic miniaturization and performance.

A paper detailing the team’s research appears in Nature Electronics.

Among microchip technologies, CMOS microchips are found in nearly all electronics, from phones and televisions to satellites and medical devices. Compared with conventional silicon chips, hybrid CMOS microchips hold greater promise for large-area electronics...

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Next-generation AI hardware: 3D photonic-electronic platform boosts efficiency and bandwidth

New study showcases 3D photonics with record performance for AI
3D photonic chip module. Credit: Keren Bergman

Artificial intelligence (AI) systems promise transformative advancements, yet their growth has been limited by energy inefficiencies and bottlenecks in data transfer. Researchers at Columbia Engineering have unveiled a groundbreaking solution: a 3D photonic-electronic platform that achieves unprecedented energy efficiency and bandwidth density, paving the way for next-generation AI hardware.

The study, “3D Photonics for Ultra-Low Energy, High Bandwidth-Density Chip Data Links,” led by Keren Bergman, Charles Batchelor Professor of Electrical Engineering, is published in Nature Photonics.

The research details a pioneering method that integrates photonics with advanced complementary-metal- oxide-semiconductor (CMOS) electronics to redef...

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Wirelessly Powered Relay will help bring 5G Technology to Smart Factories

Figure 2 Prototype of the proposed relay transceiver The prototype of the proposed relay transceiver was fabricated with Si CMOS 65nm chips and 4×2 patch phased-array antenna board.
Prototype of the proposed relay transceiver
The prototype of the proposed relay transceiver was fabricated with Si CMOS 65nm chips and 4×2 patch phased-array antenna board.

The proposed innovative design leads to unprecedented power conversion efficiency and improved versatility. A recently developed wirelessly powered 5G relay could accelerate the development of smart factories, report scientists from Tokyo Tech. By adopting a lower operating frequency for wireless power transfer, the proposed relay design solves many of the current limitations, including range and efficiency. In turn, this allows for a more versatile and widespread arrangement of sensors and transceivers in industrial settings.

One of the hallmarks of the Information Age is the transformation of industries towards...

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