CMOS tagged posts

A recent study published in Nature Electronics and carried out by researchers from nanoGUNE’s Quantum Hardware research group, Quantum Motion, London Center for Nanotechnology, Imperial College London and the University of Cambridge introduces a new superinductor created within a silicon integrated circuit fabricated in a commercial complementary metal–oxide–semiconductor (CMOS) process.

Superinductors are electrical inductors that are engineered to have an extremely large inductance, often far beyond what can be achieved with conventional coils...

A Japan–U.S. collaborative research team has demonstrated the world’s first integrated spintronic probabilistic bit, or p-bit, fabricated on a silicon chip using semiconductor manufacturing processes. The team, consisting of researchers from Tohoku University and the National Institute of Standards and Technology, experimentally verified the operation of the p-bit, a key building block for probabilistic, or p-, computers. The achievement provides a pathway toward large-scale spintronic p-computers for applications such as AI and machine learning.

Many emerging computational problems require efficient exploratio...

King Abdullah University of Science and Technology (KAUST; Saudi Arabia) researchers have set a record in microchip design, achieving the first six-stack hybrid CMOS (complementary metal-oxide semiconductor) for large-area electronics. With no other reported hybrid CMOS exceeding two stacks, the feat marks a new benchmark in integration density and efficiency, opening possibilities in electronic miniaturization and performance.

A paper detailing the team’s research appears in Nature Electronics.

Among microchip technologies, CMOS microchips are found in nearly all electronics, from phones and televisions to satellites and medical devices. Compared with conventional silicon chips, hybrid CMOS microchips hold greater promise for large-area electronics...

Artificial intelligence (AI) systems promise transformative advancements, yet their growth has been limited by energy inefficiencies and bottlenecks in data transfer. Researchers at Columbia Engineering have unveiled a groundbreaking solution: a 3D photonic-electronic platform that achieves unprecedented energy efficiency and bandwidth density, paving the way for next-generation AI hardware.

The study, “3D Photonics for Ultra-Low Energy, High Bandwidth-Density Chip Data Links,” led by Keren Bergman, Charles Batchelor Professor of Electrical Engineering, is published in Nature Photonics.

The research details a pioneering method that integrates photonics with advanced complementary-metal- oxide-semiconductor (CMOS) electronics to redef...